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71M6543F/71M6543G Data Sheet
When system power is not available, the 71M6543 is in one of three battery modes:
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BRN mode (brownout mode)
LCD mode (LCD-only mode)
SLP mode (sleep mode).
An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are
typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 2.8 VDC, the
comparator resets an internal power status bit called V3OK . As soon as system power is removed and
V3OK = 0, the 71M6543 is forced to BRN mode. The MPU continues to execute code when the system
transitions from MSN to BRN mode or from BRN to MSN mode. A soft reset should be executed when
returning from BRN to MSN mode in order to re-initialize the I/O RAM. Depending on the MPU code, the
MPU can choose to stay in BRN mode, or transition to LCD or to SLP mode (via the I/O RAM bits
LCD_ONLY , I/O RAM 0x28B2[6] and SLEEP, I/O RAM 0x28B2[7] ). BRN mode is similar to MSN mode except
that resources powered by system power, such as the ADC and the CE, are not available (see Table 61 ),
and that the supply current is drawn from the VBAT pin. In BRN mode, the PLL continues to function at
the same frequency as in MSN mode. The MPU can configure BRN mode as it desires. For instance, it
may choose to minimize battery power by reducing the PLL or MPU clock speed (see 3.2.1 BRN Mode ,
for the recommended settings to realize minimum power consumption in BRN mode).
When system power is restored, the 71M6543 automatically transitions from any of the battery modes
(BRN, LCD, SLP) back to MSN mode.
Figure 25 shows a state diagram of the various operating modes, with the possible transitions between modes.
When the part wakes-up under battery power, the part automatically enters BRN mode (see 3.4 Wake-Up
Behavior ). From BRN mode, the part may enter either LCD mode or SLP mode, as controlled by the MPU.
MSN
V3P3SYS
falls
RESET
V3P3SYS
rises
LCD_ONLY
VSTAT=00X
V3P3SYS
rises
BRN
Wake Flags
VSTAT=001
RESET &
VBAT
sufficient
System Power
Battery Power
V3P3SYS
rises
LCD
VBAT
insufficient
Wake
event
RESET &
VBAT
insufficient
Wake
event
SLEEP or
VBAT
insufficient
VBAT
insufficient
SLP
Figure 25: Operation Modes State Diagram
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